The present invention relates to a testing system for integrated circuits (ICs) and more particularly, generating clock signals for scan testing of asynchronous domains of integrated circuits.
Integrated circuits (ICs) include multiple clock domains. These clock domains include several storage elements that may vary in type and size. Each clock domain is driven by a clock signal. The clock signals provided to the various clock domains are derived from signals generated using one or more clock sources. The clock sources include components such as an external crystal oscillator, internal resistor capacitor (RC) oscillators and phase locked loops. The clock signals generated by the various clock sources may be asynchronous with respect to each other. The clock signal provided to a clock domain further is branched out through a series of buffers to form a plurality of clock signals. The structure of the branching of the clock signal is called a clock tree. For reasons such as differing clock tree builds and routing delays, any two clock signals may be offset with respect to one another. This finite difference in clock signals is called clock skew. When the storage elements clocked using the skewed clock signals communicate with each other, timing violations such as setup and hold violations may occur. To avoid setup and hold violations, the clock signal is distributed through a skew minimized network within a clock domain. Thus, the clock skew within a clock domain is minimized; however, inter-domain clock skew may still exist. The inter-domain clock skew may not interfere in the functional operation of a pair of asynchronous domains because the stability of interaction between such domains is provided by the IC design through the use of appropriate synchronizers, for example.
It is well-known that ICs are prone to various types of manufacturing defects. Structural testing paradigms, such as Design for Test (DFT), have been created to detect the occurrence of such faults. Scan-based tests form a major part of IC post-production testing. Scan-based testing may be divided into stuck-at testing and at-speed testing. Stuck-at testing detects static faults and at-speed testing detects delay faults like transition faults and path delay faults. Subsequent description is focused on stuck-at fault testing of ICs. To enable scan testing in a design, the clock signal provided to the storage elements must be controlled from an external primary input of the IC. However, due to test cost implications, mapping each functional clock domain to an independent top-level clock pin is not feasible. Hence, chip designers target using a minimum number of pins to test a device. Therefore, even though there may be multiple asynchronous functional clock domains, they are mapped to a single external pin during stuck-at testing. Performing timing closures for such architecture is challenging.
As is known in the art, a scan test includes a shift phase and a capture phase. During the shift phase, the various storage elements are configured into scan chains, and a test data sequence (test stimulus) is shifted into the scan chains through scan inputs. At the end of the shift phase, the loaded stimuli are applied to a combinatorial circuit. Subsequently, during the capture phase, functional responses of the combinational circuit to the applied test stimuli are captured in the storage elements and then shifted-out.
The test patterns used for scan testing are generated using an Automated Test Pattern Generator (ATPG) tool. These test patterns are based on assumption of an ideal clock, which means that the clock signal reaches each clock domain simultaneously without skew. However, as discussed above the clock skew between various clock domains may lead to large differences between the various clock signals used to drive the clock domains. During a scan capture operation, that may involve inter-domain communication, the clock skew may lead to data transitions associated with a first clock domain to fall in the setup or hold time window of a second clock domain, thereby causing erroneous operation. Since, scan vectors (used as test stimuli) are generated based on the zero clock skew assumption, application of the scan vectors to the design is prone to timing errors. Therefore, concurrent pulsing of all the internal scan clock domains during the capture cycle is not feasible. However, if each of the various clock domains are controlled by separate external scan clocks, concurrent pulsing of the unbalanced clock domains can be avoided by externally offsetting clock signals. This provides the first clock domain suitable time to settle before a second clock domain receives the active clock edge. Since, during stuck-at testing, the frequency of capture is not high and specifically static faults are targeted, the clock pulses may be spaced apart without impacting scan test performance. However, increasing the number of clock pins leads to a direct increase in tester resources, which in turn impacts the test cost of the device.
An alternative to the above procedure may be to enable concurrent pulsing of several internal scan clock domains by design. This implies that timing violations between such internal scan clock domains are eliminated in the physical design. This process is iterative, time consuming, and thus impacts design and design-cycle time.
Referring now to FIG. 1A, a system 100 is shown. The system 100 includes an IC 104. The IC 104 includes clock domains 106a, 106b, and 106c. The clock domain 106a includes scan chains 108a and 108b. Similarly, the clock domain 106b includes scan chains 108c and 108d and the clock domain 106c includes scan chains 108e and 108f. FIG. 1B is a timing diagram 110 illustrating an exemplary operation during scan testing of the IC 104. The timing diagram 110 includes waveforms 112a, 112b, and 112c, and a set-up and hold time window 114.
When ATPG test patterns are provided to the IC 104, the test vectors are provided to the clock domains 106a, 106b, and 106c. Thereafter, responses to the test vectors are received. The responses are output from the IC 104 and compared with expected test vector responses on an external tester (not shown) to determine whether there are any faults. Such typical scan testing progresses through the following steps: shift-in, capture, and shift-out, all of which are controlled by the test clock signal, TEST CLK. TEST CLK is provided externally through a pin of the IC 104 and distributed to the clock domains 106a, 106b, and 106c as internal clock signals CLK A, CLK B, and CLK C. During the shift-in phase of the scan test, the scan chains 108a, 108b, 108c, 108d, 108e, and 108f are loaded with test patterns at active edges of CLK A, CLK B, and CLK C. Depending on the number of scan cells in the scan chains 108a, 108b, 108c, 108d, 108e, and 108f, a certain number of TEST CLK pulses are provided for loading the scan chains with test patterns. At the last TEST CLK pulse of the shift-in phase, the test patterns are applied to the combinatorial logic circuit. Subsequently, the capture phase of the scan test is initiated. At the capture pulse, the functional responses of the combinational logic circuits are captured. Thereafter, the shift-out phase is initiated, which involves shifting the test response out of the scan cells to the scan out pins of IC 104, and to the external tester (not shown). The external tester compares the test response data with the expected “good-device” response data to differentiate between an error-free device and a faulty device.
It should be realized that for testing communication links between the first clock domain, such as the clock domain 106a and the second clock domain, such as the clock domain 106b, inter-domain communication is required. Inter-domain communication involves launching of test data from the clock domain 106a to the clock domain 106b and the receipt of the test data by the clock domain 106b to determine whether the communication channel between the clock domains 106a and 106b is damaged. The test patterns used to perform the above-mentioned test are based on the no-skew assumption between the clock signals received by the clock domains 106a and 106b. However, due to clock skew, the testing may not progress in the above described manner. A transition, shown in the waveform 112b in FIG. 1B, at the output of the clock domain 106a, may occur such that the transition falls within the set-up and hold time window 114 of the clock domain 106b. This timing error leads to erroneous data capture by the clock domain 106b, thereby hampering inter-domain testing. To avoid capture of erroneous data, timing errors needs to be eliminated. In the present state of the art, the timing errors are eliminated by including a large number of hold buffers in the IC 104. This process is iterative and cumbersome. Additionally, the large number of hold buffers increases chip area and causes the IC 104 to consume more power.
As technology nodes shrink, the variation in signal path delays becomes non-linear across different process, voltage and temperature (PVT) corners. Further, different sets of signal paths may become critical depending on the different PVT corners. The number of PVT corners also increases at such lower nodes, which makes this exercise all the more tedious. Additionally, taking into account on-chip variations (OCV) and noise further add to the effort of performing timing closure. Thus, meeting timing requirements is requiring an increasing number of iterations, thereby increasing design cycle time and new product introduction (NPI) cycle time.
Problems encountered in the system 100 depicted in FIG. 1A are resolved by either controlling external clock inputs by providing tester offsets (in case of multiple external scan clocks), or by adding delay elements in the clock signal paths. FIG. 1C illustrates an IC 120 including the clock domains 106a, 106b and 106c and the scan chains 108a-108f, as well as delay elements 122a, 122b, and 122c. The delay elements 122a, 122b, and 122c were inserted in the clock paths leading to the clock domains 106a, 106b, and 106c. The delay elements 122a-122c are configured to introduce different delays in the corresponding clock paths in order to overcome inter-domain clock skews.
FIG. 1D is a timing diagram 124 illustrating the operation of the IC 120. The timing diagram includes the waveforms 112a-112c shown in FIG. 1B as well as a waveform of adjusted CLK B 112d and a setup and hold window 116. The insertion of the delay elements 122a-122c in the clock paths increases the skew between active edges of two clock domains. The skew is deliberately increased such that a first set of flip-flops is provided with an appropriate amount of time to settle before a second set of flip-flops is pulsed. As may be observed from FIG. 1D, the transition in the waveform 112b does not fall in the setup and hold window 116 of the adjusted CLK B waveform 112d. 
The above-suggested solution eliminates the need for balancing the internal scan clocks. However, internal delay elements are capable of offsetting the clock signals only in a particular direction. Additionally, using the above approach and using a single external clock pin, various sequences of clock pulsing during capture cannot be created. For example, if CLK B is delayed more than CLK A by the delay elements, there will not be a clock sequence that pulses CLK B preceding the pulse on CLK A. Further, the above-described skew compensation technique causes the scan output data generated to be different from that predicted by the ATPG tool, as the ATPG tool is not timing aware. Therefore, the scan vectors need post-processing. It would be advantageous to be able to close timing violations and be able to determine stuck-at faults without overly impacting design time, IC real estate, and IC power consumption.